diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-09-07 16:00:40 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-09-11 15:26:01 -0700 |
| commit | 49ad316f87f17b8eaf6985c7baac7bc069dccddc (patch) | |
| tree | aa413a1a3efb99138b6d09264cefac9561c45e34 /drivers/gpu/drm/i915/intel_psr.c | |
| parent | 2a5db87f82cb6b2763d5e07cc4eef8cd94e56395 (diff) | |
drm/i915/psr: Add enable_sink vfunc.
Continue on VLV PSR split with vfunc, let's also create one
for enabling sink.
v2: Fix typo on commit message (DK).
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-11-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_psr.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 2516d2a50022..02c32cc38648 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -541,17 +541,12 @@ void intel_psr_enable(struct intel_dp *intel_dp, dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.setup_vsc(intel_dp, crtc_state); + dev_priv->psr.enable_sink(intel_dp); if (HAS_DDI(dev_priv)) { - /* Enable PSR on the panel */ - hsw_psr_enable_sink(intel_dp); - hsw_psr_enable_source(intel_dp, crtc_state); } else { - /* Enable PSR on the panel */ - vlv_psr_enable_sink(intel_dp); - vlv_psr_enable_source(intel_dp, crtc_state); } @@ -979,10 +974,12 @@ void intel_psr_init(struct drm_i915_private *dev_priv) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv->psr.disable_source = vlv_psr_disable; + dev_priv->psr.enable_sink = vlv_psr_enable_sink; dev_priv->psr.activate = vlv_psr_activate; dev_priv->psr.setup_vsc = vlv_psr_setup_vsc; } else { dev_priv->psr.disable_source = hsw_psr_disable; + dev_priv->psr.enable_sink = hsw_psr_enable_sink; dev_priv->psr.activate = hsw_psr_activate; dev_priv->psr.setup_vsc = hsw_psr_setup_vsc; } |