diff options
| author | Ville Syrjälä <[email protected]> | 2015-06-24 22:00:07 +0300 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2015-06-29 10:58:07 +0200 |
| commit | 852eb00dc44ea2b8896e2fa27c6a36a1f697ba5a (patch) | |
| tree | c2e594cd97cdf6c656285e789639c0caf07699c4 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 26e1fe4fbd4c15919f8cfa9440d70eca5a457ba3 (diff) | |
drm/i915: Try to make sure cxsr is disabled around plane enable/disable
CxSR (or maxfifo on VLV/CHV) blocks somne changes to the plane control
register (enable bit at least, not quite sure about the rest). So in
order to have the plane enable/disable when we want we need to first
kick the hardware out of cxsr.
Unfortunateloy this requires some extra vblank waits. For the CxSR
enable after the plane update we should eventually use an async
vblank worker, but since we don't have that just do sync vblank
waits. For the disable case we have no choice but to do it
synchronously.
Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Clint Taylor <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0cccc44e1828..a023b40c046b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -335,6 +335,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) if (IS_VALLEYVIEW(dev)) { I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); POSTING_READ(FW_BLC_SELF_VLV); + dev_priv->wm.vlv.cxsr = enable; } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); POSTING_READ(FW_BLC_SELF); @@ -1116,7 +1117,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc) memset(wm_state, 0, sizeof(*wm_state)); - wm_state->cxsr = crtc->pipe != PIPE_C; + wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; if (IS_CHERRYVIEW(dev)) wm_state->num_levels = CHV_WM_NUM_LEVELS; else @@ -1369,10 +1370,8 @@ static void vlv_update_wm(struct drm_crtc *crtc) dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) chv_set_memory_pm5(dev_priv, false); - if (!wm.cxsr && dev_priv->wm.vlv.cxsr) { + if (!wm.cxsr && dev_priv->wm.vlv.cxsr) intel_set_memory_cxsr(dev_priv, false); - intel_wait_for_vblank(dev, pipe); - } /* FIXME should be part of crtc atomic commit */ vlv_pipe_set_fifo_size(intel_crtc); @@ -1385,10 +1384,8 @@ static void vlv_update_wm(struct drm_crtc *crtc) wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); - if (wm.cxsr && !dev_priv->wm.vlv.cxsr) { - intel_wait_for_vblank(dev, pipe); + if (wm.cxsr && !dev_priv->wm.vlv.cxsr) intel_set_memory_cxsr(dev_priv, true); - } if (wm.level >= VLV_WM_LEVEL_PM5 && dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) |