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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-03-28 14:57:57 -0700 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-04-27 17:23:01 -0700 |
| commit | 78b60ce7b96cf1869b51cee916a40041e400d6ce (patch) | |
| tree | 2e8d60b2c2c3b722442c275cbffdca9d6b9f5a36 /drivers/gpu/drm/i915/intel_engine_cs.c | |
| parent | 37cde11ba720cc485bbc784e9a34878d40a34e96 (diff) | |
drm/i915/icl: add definitions for the ICL PLL registers
There's a lot of code for the PLL enabling, so let's first only
introduce the register definitions in order to make patch reviewing a
little easier.
v2: Coding style (Jani).
v3: Preparation for upstreaming.
v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James).
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328215803.13835-3-paulo.r.zanoni@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_engine_cs.c')
0 files changed, 0 insertions, 0 deletions