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authorVille Syrjälä <[email protected]>2015-06-24 22:00:06 +0300
committerDaniel Vetter <[email protected]>2015-06-29 10:56:03 +0200
commit26e1fe4fbd4c15919f8cfa9440d70eca5a457ba3 (patch)
tree7585af5e0101c098021354980dc893b0c7dd8232 /drivers/gpu/drm/i915/intel_display.c
parent54f1b6e15db87722aa21035169ce811af9d971fd (diff)
drm/i915: Use the memory latency based WM computation on VLV too
In order to get decnet memory self refresh residency on VLV, flip it over to the new CHV way of doing things. VLV doesn't do PM5 or DDR DVFS so it's a bit simpler. I'm not sure the currently memory latency used for CHV is really appropriate for VLV. Some further testing will probably be needed to figure that out. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7baa45db9756..649c5dba5463 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15455,7 +15455,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
pll->on = false;
}
- if (IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev))
vlv_wm_get_hw_state(dev);
else if (IS_GEN9(dev))
skl_wm_get_hw_state(dev);