Merge tag 'drm-intel-next-2016-02-29' of git://anongit.freedesktop.org/drm-intel into drm-next

- fbc by default on hsw&bdw, thanks to great work by Paulo!
- psr by default hsw,bdw,vlv&chv, thanks to great work by Rodrigo!
- fixes to hw state readout vs. rpm issues (Imre)
- dc3 fixes&improvements (Mika), this and above already cherr-pick to -fixes
- first part of locking fixes from Tvrtko
- proper atomic code for load detect (Maarten)
- more rpm fixes from Ville
- more atomic work from Maarten

* tag 'drm-intel-next-2016-02-29' of git://anongit.freedesktop.org/drm-intel: (63 commits)
  drm/i915: Update DRIVER_DATE to 20160229
  drm/i915: Execlists cannot pin a context without the object
  drm/i915: Reduce the pointer dance of i915_is_ggtt()
  drm/i915: Rename vma->*_list to *_link for consistency
  drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
  drm/i915/lrc: Only set RS ctx enable in ctx control reg if there is a RS
  drm/i915/gen9: Set value of Indirect Context Offset based on gen version
  drm/i915: Remove update_sprite_watermarks.
  drm/i915: Kill off intel_crtc->atomic.wait_vblank, v6.
  drm/i915: Unify power domain handling.
  drm/i915: Pass crtc state to modeset_get_crtc_power_domains.
  drm/i915: Add for_each_pipe_masked()
  drm/i915: Make sure pipe interrupts are processed before turning off power well on BDW+
  drm/i915: synchronize_irq() before turning off disp2d power well on VLV/CHV
  drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is down
  drm/i915/gen9: Write dc state debugmask bits only once
  drm/i915/gen9: Extend dmc debug mask to include cores
  drm/i915/gen9: Verify and enforce dc6 state writes
  drm/i915/gen9: Check for DC state mismatch
  drm/i915/fbc: enable FBC by default on HSW and BDW
  ...

1 files changed, 7 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 2a7ec3141c8d..902054efb902 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -220,19 +220,19 @@ static const struct stepping_info *intel_get_stepping_info(struct drm_device *de
  * Everytime display comes back from low power state this function is called to
  * copy the firmware from internal memory to registers.
  */
-void intel_csr_load_program(struct drm_i915_private *dev_priv)
+bool intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
 	u32 *payload = dev_priv->csr.dmc_payload;
 	uint32_t i, fw_size;
 
 	if (!IS_GEN9(dev_priv)) {
 		DRM_ERROR("No CSR support available for this platform\n");
-		return;
+		return false;
 	}
 
 	if (!dev_priv->csr.dmc_payload) {
 		DRM_ERROR("Tried to program CSR with empty payload\n");
-		return;
+		return false;
 	}
 
 	fw_size = dev_priv->csr.dmc_fw_size;
@@ -243,6 +243,10 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 		I915_WRITE(dev_priv->csr.mmioaddr[i],
 			   dev_priv->csr.mmiodata[i]);
 	}
+
+	dev_priv->csr.dc_state = 0;
+
+	return true;
 }
 
 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,