diff options
author | Madhav Chauhan <madhav.chauhan@intel.com> | 2018-07-05 19:19:35 +0530 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2018-07-06 12:14:15 +0300 |
commit | b1cb21a5f1c668534b25464717c806e141ba500f (patch) | |
tree | 164cd53847f6a4f6ddc81aba44bf24000f3f95f7 /drivers/gpu/drm/i915/icl_dsi.c | |
parent | 21652f3b0d48749e3ba0d332d2b39cc18eacb1c0 (diff) |
drm/i915/icl: Enable DSI IO power
This patch configures mode of operation for DSI
and enable DDI IO power by configuring power well.
v2: Use for_each_dsi_port() for power get (Jani N)
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530798591-2077-5-git-send-email-madhav.chauhan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/icl_dsi.c')
-rw-r--r-- | drivers/gpu/drm/i915/icl_dsi.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 1eb4ac30e400..774ab262c8f3 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -54,11 +54,34 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder) } } +static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + enum port port; + u32 tmp; + + for_each_dsi_port(port, intel_dsi->ports) { + tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); + tmp |= COMBO_PHY_MODE_DSI; + I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); + } + + for_each_dsi_port(port, intel_dsi->ports) { + intel_display_power_get(dev_priv, port == PORT_A ? + POWER_DOMAIN_PORT_DDI_A_IO : + POWER_DOMAIN_PORT_DDI_B_IO); + } +} + static void __attribute__((unused)) gen11_dsi_pre_enable(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { + /* step2: enable IO power */ + gen11_dsi_enable_io_power(encoder); + /* step3: enable DSI PLL */ gen11_dsi_program_esc_clk_div(encoder); } |