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authorJani Nikula <jani.nikula@intel.com>2024-06-04 18:26:15 +0300
committerJani Nikula <jani.nikula@intel.com>2024-06-07 11:29:02 +0300
commit2d557d3abafb92b813f8dff613c9fd54161cbbc8 (patch)
treeadf312f4882c76021df646a5d302d518eda73cfc /drivers/gpu/drm/i915/i915_reg.h
parent04f657cf6677d7606c2ebcb6d8643cec0ec683c7 (diff)
drm/i915: pass dev_priv explicitly to PIPE_LINK_N2
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_N2 register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5267c167414fb46a25277c1c9a802f6ccf8de3c9.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0e9cc998143..5f822b8f1775 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2305,7 +2305,7 @@
#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
-#define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
+#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
/* CPU panel fitter */
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */