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| author | Matthew Auld <matthew.auld@intel.com> | 2019-08-09 20:34:55 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-08-10 13:18:32 +0100 |
| commit | 1feb7864b2cbd874a677ce04d61834d5664133ab (patch) | |
| tree | 8bc62abd733909cab90a4766ea3e2f2b3f724a2a /drivers/gpu/drm/i915/i915_pci.c | |
| parent | 18851edfa7dbe156cfc5a73bf009d8a4def84bb5 (diff) | |
drm/i915/gtt: enable GTT cache by default
For some platforms the GTT cache is by default not enabled, and
currently where we explicitly enable it, we make it conditional on 2M GTT
page support, since the BSpec states that we must disable it if we
enable 2M/1G pages. To make this more consistent opt for blanket
enabling the GTT cache for all relevant gens in a single place, while
still keeping the same behaviour of checking for 2M support.
BSpec: 9314
BSpec: 423
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190809193456.3836-1-matthew.auld@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_pci.c')
0 files changed, 0 insertions, 0 deletions