diff options
author | Michel Thierry <michel.thierry@intel.com> | 2018-04-05 17:00:48 +0300 |
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committer | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2018-04-06 15:33:04 +0300 |
commit | e34b0345e6a531f980a6560fdc3b651de9cfcc67 (patch) | |
tree | 23cab34e8b16b3434a478a930a089eda4b18a0aa /drivers/gpu/drm/i915/i915_irq.c | |
parent | 99d7e4eeea778374ecea279d0379fbecb0b297bf (diff) |
drm/i915/icl: Add reset control register changes
The bits used to reset the different engines/domains have changed in
GEN11, this patch maps the reset engine mask bits with the new bits
in the reset control register.
v2: Use shift-left instead of BIT macro to match the file style (Paulo).
v3: Reuse gen8_reset_engines (Daniele).
v4: Do not call intel_uncore_forcewake_reset after reset, we may be
using the forcewake to read protected registers elsewhere and those
results may be clobbered by the concurrent dropping of forcewake.
bspec: 19212
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180405140052.10682-1-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
0 files changed, 0 insertions, 0 deletions