diff options
| author | John Harrison <John.C.Harrison@Intel.com> | 2023-01-11 12:04:29 -0800 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2023-01-17 15:28:28 -0800 |
| commit | 67804e48b4945e109b54b4bf5a75f5cad3e2dca0 (patch) | |
| tree | 528f373dddac997b456dbea5666cf73fefadea11 /drivers/gpu/drm/i915/gt/intel_gt_mcr.c | |
| parent | 0c8a6e9ea232c221976a0670256bd861408d9917 (diff) | |
drm/i915/gt: Start adding module oriented dmesg output
When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a GT# prefix on it.
v2: Go back to using lower case names (combined review feedback).
Convert intel_gt.c as a first step.
v3: Add gt_err_ratelimited() as well, undo one conversation that might
not have a GT pointer in some scenarios (review feedback from Michal W).
Split definitions into separate header (review feedback from Jani).
Convert all intel_gt*.c files.
v4: Re-order some macro definitions (Andi S), update (c) date (Tvrtko)
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230111200429.2139084-2-John.C.Harrison@Intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gt_mcr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index 4127830c33ca..169393a7ad88 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -6,6 +6,7 @@ #include "i915_drv.h" #include "intel_gt_mcr.h" +#include "intel_gt_print.h" #include "intel_gt_regs.h" /** @@ -158,7 +159,7 @@ void intel_gt_mcr_init(struct intel_gt *gt) GEN12_MEML3_EN_MASK); if (!gt->info.mslice_mask) /* should be impossible! */ - drm_warn(&i915->drm, "mslice mask all zero!\n"); + gt_warn(gt, "mslice mask all zero!\n"); } if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) { @@ -205,7 +206,7 @@ void intel_gt_mcr_init(struct intel_gt *gt) ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & GEN10_L3BANK_MASK; if (!gt->info.l3bank_mask) /* should be impossible! */ - drm_warn(&i915->drm, "L3 bank mask is all zero!\n"); + gt_warn(gt, "L3 bank mask is all zero!\n"); } else if (GRAPHICS_VER(i915) >= 11) { /* * We expect all modern platforms to have at least some @@ -394,9 +395,7 @@ void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags) * releasing it properly. */ if (err == -ETIMEDOUT) { - drm_err_ratelimited(>->i915->drm, - "GT%u hardware MCR steering semaphore timed out", - gt->info.id); + gt_err_ratelimited(gt, "hardware MCR steering semaphore timed out"); add_taint_for_CI(gt->i915, TAINT_WARN); /* CI is now unreliable */ } } |