diff options
| author | Ville Syrjälä <[email protected]> | 2022-10-31 15:57:00 +0200 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2022-11-02 08:53:59 +0200 |
| commit | dbea79a50221899e2c3b4be9967f535e89fd6d00 (patch) | |
| tree | d82673ad267d716704810e0dfa7df4b69ba4cdf5 /drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | |
| parent | 78e418d0ea7f74bca0c2312281a28de831ae8edf (diff) | |
drm/i915: Fix cs timestamp frequency for cl/bw
Despite what the spec says the TIMESTAMP register seems to
tick once every hrawclk (confirmed on i965gm and g35).
v2: Rebase
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 23a27e49b898..2a6a4ca7fdad 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -147,8 +147,10 @@ static u32 gen4_read_clock_frequency(struct intel_uncore *uncore) * "The value in this register increments once every 16 * hclks." (through the “Clocking Configuration” * (“CLKCFG”) MCHBAR register) + * + * Testing on actual hardware has shown there is no /16. */ - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16; + return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000; } static u32 read_clock_frequency(struct intel_uncore *uncore) |