diff options
| author | Imre Deak <imre.deak@intel.com> | 2021-10-27 01:51:04 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2021-11-02 18:07:59 +0200 |
| commit | 17749ece0142c7c368834b6fb35d86bafecef69f (patch) | |
| tree | a62621dc4d02277ea493fd1bfa8c724f163034ee /drivers/gpu/drm/i915/display/intel_fb.c | |
| parent | be6c1dd5ac074defdfb1471d28e0bb6eedfe3ae5 (diff) | |
drm/i915/adlp/fb: Remove restriction on semiplanar UV plane offset
Since the surfaces of tiled FBs on ADLP are remapped it's pointless to
require an alignment in the allocated object. The necessary tile-row
alignment (to be programmed to the surface start register) will be
ensured later when flipping to the FB.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211026225105.2783797-7-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_fb.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fb.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index e0414fb4b036..c19a5f881644 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1018,6 +1018,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, u32 alignment; if (DISPLAY_VER(i915) >= 12 && + !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) && is_semiplanar_uv_plane(fb, color_plane)) alignment = intel_tile_row_size(fb, color_plane); else if (fb->modifier != DRM_FORMAT_MOD_LINEAR) |