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authorDmitry Torokhov <[email protected]>2020-01-10 14:56:04 -0800
committerDmitry Torokhov <[email protected]>2020-01-10 14:56:04 -0800
commit1bdd3e05a0a3b4a97ea88bc46fef8fb265c8b94c (patch)
tree2244894a9ea0c941a8f32e5f3d196b4ea0eae24b /drivers/gpu/drm/i915/display/intel_dvo.c
parent643dd7416649bea2e8c61d8fdeeefb409a0ca5eb (diff)
parentc79f46a282390e0f5b306007bf7b11a46d529538 (diff)
Merge tag 'v5.5-rc5' into next
Sync up with mainline to get SPI "delay" API changes.
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dvo.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dvo.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 93baf366692e..bcfbcb743e7d 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -280,7 +280,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
- int pipe = crtc->pipe;
+ enum pipe pipe = crtc->pipe;
u32 dvo_val;
i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
@@ -505,7 +505,7 @@ void intel_dvo_init(struct drm_i915_private *dev_priv)
intel_encoder->type = INTEL_OUTPUT_DVO;
intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
intel_encoder->port = port;
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
+ intel_encoder->pipe_mask = ~0;
switch (dvo->type) {
case INTEL_DVO_CHIP_TMDS: