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| author | Ville Syrjälä <[email protected]> | 2021-10-06 23:49:37 +0300 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2021-10-28 21:20:00 +0300 |
| commit | ead3ea12e133416fbd800eedb2fb5d0faf2df431 (patch) | |
| tree | 8009d1e89c8353eca8a65d175c8b9d8442963e78 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | 32c2bc89c7420fad2959ee23ef5b6be8b05d2bde (diff) | |
drm/i915: Fix icl+ combo phy static lane power down setup
Our lane power down defines already include the necessary shift,
don't shift them a second time.
Fortunately we masked off the correct bits, so we accidentally
left all lanes powered up all the time.
Bits 8-11 where we end up writing our misdirected lane mask are
documented as MBZ, but looks like you can actually write there
so they're not read only bits. No idea what side effect the
bogus register write might have.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4151
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Imre Deak <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions