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author | Ville Syrjälä <[email protected]> | 2020-09-08 17:02:10 +0300 |
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committer | Ville Syrjälä <[email protected]> | 2020-09-14 16:20:57 +0300 |
commit | 8dec2fc11b8cdad7d2b5679ebf0b742d511eacae (patch) | |
tree | fddfce4d92e9ff861cd9931990dfdaf39b42ef0c /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
parent | b41e58ffe49172eb260e95c217d3e1f0f7432ba6 (diff) |
drm/i915: Nuke CACHE_MODE_0 save/restore
The CACHE_MODE_0 save/restore was added without explanation in
commit 1f84e550a870 ("drm/i915 more registers for S3 (DSPCLK_GATE_D,
CACHE_MODE_0, MI_ARB_STATE)"). If there are any bits we care about
those should be set explicitly during some appropriate init function.
Let's assume it's all good and just nuke this magic save/restore.
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Acked-by: Jani Nikula <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions