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authorAnkit Nautiyal <[email protected]>2021-08-11 10:48:57 +0530
committerUma Shankar <[email protected]>2021-08-11 18:36:07 +0530
commit70418a68713c13da3f36c388087d0220b456a430 (patch)
tree15bea5b3c1617220844d3d1bafbd32541b7fb01f /drivers/gpu/drm/i915/display/intel_dp_mst.c
parent3bfa7d40ce736ffbbfe07127061f54b359ee2b12 (diff)
drm/i915/display: Fix the 12 BPC bits for PIPE_MISC reg
Till DISPLAY12 the PIPE_MISC bits 5-7 are used to set the Dithering BPC, with valid values of 6, 8, 10 BPC. For ADLP+ these bits are used to set the PORT OUTPUT BPC, with valid values of: 6, 8, 10, 12 BPC, and need to be programmed whether dithering is enabled or not. This patch: -corrects the bits 5-7 for PIPE MISC register for 12 BPC. -renames the bits and mask to have generic names for these bits for dithering bpc and port output bpc. v3: Added a note for MIPI DSI which uses the PIPE_MISC for readout for pipe_bpp. (Uma Shankar) v2: Added 'display' to the subject and fixes tag. (Uma Shankar) Fixes: 756f85cffef2 ("drm/i915/bdw: Broadwell has PIPEMISC") Cc: Paulo Zanoni <[email protected]> (v1) Cc: Ville Syrjälä <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: [email protected] Cc: <[email protected]> # v3.13+ Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
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