diff options
| author | Jani Nikula <[email protected]> | 2021-09-09 15:51:59 +0300 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2021-09-20 18:46:05 +0300 |
| commit | 078397bbad2d70cef41771322801b73b39daddb3 (patch) | |
| tree | c9257a7a9c249c1f4fec85cf91a15b8685080f83 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | 4e718a0e4053249c0ff5df60f8f3799fce1a1981 (diff) | |
drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.
v2: Use intel_dp_is_uhbr
Reviewed-by: Manasi Navare <[email protected]> # v1
Signed-off-by: Jani Nikula <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/723b29223dc570c8b63c3c6fe5fb772d9db06c0d.1631191763.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions