diff options
| author | Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> | 2023-09-19 12:21:26 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-09-21 08:18:07 -0700 |
| commit | c2d9d8e7ee157f0ef78bcf5c0df149a4a03ae1cd (patch) | |
| tree | 679d8ec36155d9daf1cb6451c1f80b1c987f3feb /drivers/gpu/drm/i915/display/intel_dp_aux_regs.h | |
| parent | 394b4b7df9f791dc2dcc95f29cda0961900da6e9 (diff) | |
drm/i915/xe2lpd: Add display power well
Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+,
so reuse the code. PGPICA1 contains type-C capable port slices
which requires the well to power powered up, so add new power well
definition for it.
The DC_OFF fake power well will be added in a follow up commit.
v2: Do not rmw as bit 31 is the only R/W bit in the register (Matt Roper)
BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-20-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_aux_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_aux_regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h index 844369f91788..34f6e0a48ed2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h @@ -86,4 +86,9 @@ _XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \ _XELPDP_DP_AUX_CH_DATA(aux_ch, i)) +/* PICA Power Well Control */ +#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04) +#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31) +#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30) + #endif /* __INTEL_DP_AUX_REGS_H__ */ |