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| author | Jouni Högander <jouni.hogander@intel.com> | 2024-06-07 16:49:10 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2024-06-11 13:02:10 +0300 |
| commit | 32f0045f905c3cc17e8c6ae81959b3db95bb0091 (patch) | |
| tree | 5f5f25e0848f64a594f39627930f33523017918b /drivers/gpu/drm/i915/display/intel_alpm.c | |
| parent | 91930fc0394b3b54c6a8a3333b2b52c923cf6c52 (diff) | |
drm/i915/psr: Split enabling sink for PSR and Panel Replay
Current intel_psr_enable_sink is a mess due to partly reusing PSR bit
definitions for Panel Replay. Even thought PSR and Panel Replay enable
registers do have common bits they still have also different bits and same
bits with different meaning. For sake of clarity split enabling sink to PSR
and Panel Replay specific parts.
Also fix issue caused by using psr->panel_replay_enabled to early.
Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-7-jouni.hogander@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_alpm.c')
0 files changed, 0 insertions, 0 deletions