diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2019-06-25 08:54:21 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-25 12:08:46 -0500 |
| commit | 3e10f3196b55f3ed41a2727e9720c19e5ff1078f (patch) | |
| tree | d61bc77edda6df703b086aa868ee93d2bf01fc0b /drivers/gpu/drm/amd | |
| parent | 44ff0ae6b15e78565199a4c295de2a5bac425922 (diff) | |
drm/amdgpu/display: switch udelay to msleep
We may need to sleep for up to 80ms
(8ms per each of up to 10 loop iterations):
/* First DPCD read after VDD ON can fail if the particular board
* does not have HPD pin wired correctly. So if DPCD read fails,
* which it should never happen, retry a few times. Target worst
* case scenario of 80 ms.
*/
Switch udelay to msleep to avoid limits on arm.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index d6f8be654c2e..c17db5c144aa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -550,7 +550,7 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link) break; } - udelay(8000); + msleep(8); } ASSERT(status == DC_OK); |