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author | Wenjing Liu <Wenjing.Liu@amd.com> | 2020-02-18 17:11:50 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-03-05 00:29:57 -0500 |
commit | df8e34ac27e8a0d8dce364628226c5619693c3fd (patch) | |
tree | 1c3967694eb3e61d093a078ba21a089f2130f4a8 /drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | |
parent | 10b4e64e58b4a9d7669bc6682b3fd12ae62744b2 (diff) |
drm/amd/display: fix image corruption with ODM 2:1 DSC 2 slice
[why]
When combining two or more pipes in DSC mode, there will always be more
than 1 slice per line. In this case, as per DSC rules, the sink device
is expecting that the ICH is reset at the end of each slice line (i.e.
ICH_RESET_AT_END_OF_LINE must be configured based on the number of
slices at the output of ODM). It is recommended that software set
ICH_RESET_AT_END_OF_LINE = 0xF for each DSC in the ODM combine. However
the current code only set ICH_RESET_AT_END_OF_LINE = 0xF when number of
slice per DSC engine is greater than 1 instead of number of slice per
output after ODM combine.
[how]
Add is_odm in dsc config. Set ICH_RESET_AT_END_OF_LINE = 0xF if either
is_odm or number of slice per DSC engine is greater than 1.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h')
0 files changed, 0 insertions, 0 deletions