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authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2019-10-24 16:07:43 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-11-19 10:12:53 -0500
commit1c40428ace2eba5144b3f13f91df4a0c0422c68d (patch)
tree1a0db796524284822fe580e677d0ab7024f0bfe7 /drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
parent02837a91ae7584e2ac13df816bd0e82bc71ebe73 (diff)
drm/amd/display: use drm defines for MAX CASCADE MASK
[Why] drm already has this define [How] drm Mask is 0x08 vs 0x0800. The reason is because drm mask works on a byte. ^^ =======|| || Since the first byte is always zero we can ignore it and only check the second byte. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h')
-rw-r--r--drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
index bfb32afc1868..f6bba487d1d4 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h
@@ -35,8 +35,6 @@
/* TODO:
* Replace below defines with these
*
- * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
- * #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
* #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
* #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
* #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
@@ -46,8 +44,6 @@
* split the HDMI rxstatus into 2bytes before we can use usptream defs
*/
-#define BSTATUS_MAX_CASCADE_EXCEEDED_MASK 0x0800
-#define BINFO_MAX_CASCADE_EXCEEDED_MASK_DP 0x0800
#define RXSTATUS_MSG_SIZE_MASK 0x03FF
#define RXSTATUS_READY_MASK 0x0400
#define RXSTATUS_REAUTH_REQUEST_MASK 0x0800