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| author | Tony Cheng <tony.cheng@amd.com> | 2017-07-14 13:42:23 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:15:16 -0400 |
| commit | d65359d571aa33dee9ddae659e92d1cb09ffbb2a (patch) | |
| tree | 4db612a5c7132d36639cf7f523d4a6c40e9e04a7 /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | 15e173352eeae76286e0d018f9eec6b55726caa4 (diff) | |
drm/amd/display: revert order change of HUBP and MPC disable
- root cause was we disable opp clk in MPC disconnect
- hubp_blank is not double buffered, so we can't blank until MPC disconnect or we have risk of underflow
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions