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| author | Charlene Liu <charlene.liu@amd.com> | 2018-12-19 13:47:19 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-01-14 15:41:39 -0500 |
| commit | 9983b80053e4fd3d5dea7b936aa933edd49924ce (patch) | |
| tree | 29aaae9327178f91ca3413ba1fa7dbb62944e2b1 /drivers/gpu/drm/amd/display/modules/freesync/freesync.c | |
| parent | 570744b98ca865d95bdf2da064a7a57f2655f889 (diff) | |
drm/amd/display: dp interlace MSA timing programming for Interlace mode.
[Why]
DP compliance box shows wrong MSA data.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/freesync/freesync.c')
0 files changed, 0 insertions, 0 deletions