diff options
| author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-09-29 14:52:09 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-12 14:02:51 -0400 |
| commit | 36d26912e8d854853e3cdb300664db274a6636cf (patch) | |
| tree | 7bfd642a153170007b90816aae1bb561d8b66481 /drivers/gpu/drm/amd/display/include/dal_asic_id.h | |
| parent | 4da678390890c7cf99e068ecd9d7ee5bf0d5290b (diff) | |
drm/amd/display: Add support for DCN302 (v2)
- add DCN302 resource, irq service, dmub loader,
- handle DC_VERSION_DCN_3_02
- define DCN302 power gating functions
- handle DCN302 in GPIO files
- define I2C regs
- add CONFIG_DRM_AMD_DC_DCN3_02 guard
v2: rebase fixes (Alex)
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/include/dal_asic_id.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index b6b60a9c0509..e4f24dbb2572 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -195,6 +195,7 @@ enum { NV_NAVI12_P_A0 = 10, NV_NAVI14_M_A0 = 20, NV_SIENNA_CICHLID_P_A0 = 40, + NV_DIMGREY_CAVEFISH_P_A0 = 60, NV_UNKNOWN = 0xFF }; @@ -203,7 +204,10 @@ enum { #define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0)) #if defined(CONFIG_DRM_AMD_DC_DCN3_0) -#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0)) +#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0)) +#endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_02) +#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN)) #endif #if defined(CONFIG_DRM_AMD_DC_DCN3_01) #define FAMILY_VGH 144 |