drm/amd/display: move public dc link function implementation to dc_link_exports

[why]
Link is a subcomponent in dc. DM should be aware of dc link structure
as one of the abstracted objects maintained by dc. However it should
have no idea of the existence of a link component in dc dedicated to
maintain the states of dc link structure. As such we are moving link interfaces
out of dc_link.h and directly added to dc.h. We are grandually fading out
the explicit inclusion of dc_link header and eventually delete it.

On dc side, since link is a subcomponent behind dc interfaces, it is not
a good idea to implement dc interfaces in each individual subcomponent
of link which is already a subcomponent of dc. So we are decoupling it
by implementing a dc_link_exports in dc. This file will be a thin
translation layer that breaks the dependency so link is able to make
interface changes without breaking DM.

Reviewed-by: Jun Lei <[email protected]>
Acked-by: Qingqing Zhuo <[email protected]>
Signed-off-by: Wenjing Liu <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

1 files changed, 7 insertions, 7 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
index 8ddebf3bdd46..d4f6ee6ca948 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c
@@ -218,20 +218,20 @@ static bool dp_active_dongle_validate_timing(
 	return true;
 }
 
-uint32_t dc_link_bandwidth_kbps(
+uint32_t dp_link_bandwidth_kbps(
 	const struct dc_link *link,
-	const struct dc_link_settings *link_setting)
+	const struct dc_link_settings *link_settings)
 {
 	uint32_t total_data_bw_efficiency_x10000 = 0;
 	uint32_t link_rate_per_lane_kbps = 0;
 
-	switch (link_dp_get_encoding_format(link_setting)) {
+	switch (link_dp_get_encoding_format(link_settings)) {
 	case DP_8b_10b_ENCODING:
 		/* For 8b/10b encoding:
 		 * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
 		 * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
 		 */
-		link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
+		link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
 		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
 		if (dc_link_should_enable_fec(link)) {
 			total_data_bw_efficiency_x10000 /= 100;
@@ -243,7 +243,7 @@ uint32_t dc_link_bandwidth_kbps(
 		 * link rate is defined in the unit of 10mbps per lane.
 		 * total data bandwidth efficiency is always 96.71%.
 		 */
-		link_rate_per_lane_kbps = link_setting->link_rate * 10000;
+		link_rate_per_lane_kbps = link_settings->link_rate * 10000;
 		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
 		break;
 	default:
@@ -251,10 +251,10 @@ uint32_t dc_link_bandwidth_kbps(
 	}
 
 	/* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
-	return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
+	return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000;
 }
 
-uint32_t dc_bandwidth_in_kbps_from_timing(
+uint32_t link_timing_bandwidth_kbps(
 	const struct dc_crtc_timing *timing)
 {
 	uint32_t bits_per_channel = 0;