diff options
| author | Ilya Bakoulin <Ilya.Bakoulin@amd.com> | 2019-04-09 11:50:38 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:10 -0500 |
| commit | fbc9ca671f4ffbc0c873de17cf2305ca438cb09e (patch) | |
| tree | 5ecb5a259a0835afca9af67e9dfa8a8fbdad71f9 /drivers/gpu/drm/amd/display/dc/inc/hw | |
| parent | 2a874fa0257ac834142e0570a2bec629421ee031 (diff) | |
drm/amd/display: Fix ODM combine data format
[Why]
OPTC data format was left at its default value (444) when enabling
ODM combine. This caused issues with FPGA capture.
[How]
Write the OPTC_DATA_FORMAT field when enabling ODM combine.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 2dee10f7f1fe..5e93bc0e8ff9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -268,7 +268,8 @@ struct timing_generator_funcs { uint32_t dsc_slice_width); #endif void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing); - void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id, int mpcc_hactive); + void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id, + int mpcc_hactive, enum dc_pixel_encoding pixel_encoding); void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); void (*set_gsl_source_select)(struct timing_generator *optc, int group_idx, |