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authorAlvin <Alvin.Lee2@amd.com>2022-05-12 16:49:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-06-01 15:56:48 -0400
commitf0ad66f42a3d914ac5f9972731ec5bc97f35002d (patch)
tree12efa3da29300a38b15ba6acf47b17a5e4f1f8ae /drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
parent6ecf9773a5030aa4932096754bacff20e1b944b8 (diff)
drm/amd/display: Don't clear ref_dtbclk value
[Description] ref_dtbclk value is assigned in clk_mgr_construct, but the clks struct is cleared in init_clocks. Make sure to restore the value or we will get 0 value for ref_dtbclk in DCN31. Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 0eb89e117a6a..bbc58d167c63 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -572,9 +572,6 @@ static void dccg31_set_dtbclk_dto(
PIPE_DTO_SRC_SEL[params->otg_inst], 0,
DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div);
- REG_WRITE(DTBCLK_DTO_MODULO[dtbclk_inst], 0);
- REG_WRITE(DTBCLK_DTO_PHASE[dtbclk_inst], 0);
-
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
}