diff options
| author | Martin Tsai <martin.tsai@amd.com> | 2021-06-08 13:48:32 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-21 17:45:14 -0400 |
| commit | 068312559d33d90b2802561df7bff35ed407cd73 (patch) | |
| tree | 27dc186e3a871b2c959bd61a7cb1078d244cb3e0 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | |
| parent | 5d9e7fe8ef9b1c91a4821eef4533f4010e011117 (diff) | |
drm/amd/display: Clear lane settings after LTTPRs have been trained
[Why]
The voltage swing has to start from the minimum level when transmit TPS1 over
Main-Link in clock recovery sequence.
The lane settings from current design will inherit the existing VS/PE values
that could be adjusted by Repeater X, and to use the adjusted voltage swing level
in Repeater X-1 or DPRX could violate DP specs.
[How]
To reset VS from lane settings after LTTPRs have been trained to meet the requirement.
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h')
0 files changed, 0 insertions, 0 deletions