diff options
| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2018-07-17 14:11:00 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-07-18 17:47:45 -0700 |
| commit | dbda5111e2d85ff67452e9f8b82fc9eee73a224c (patch) | |
| tree | 0076715511dd9bc917dffede27c67f4c4f3b7068 /drivers/gpu/drm/amd/amdgpu | |
| parent | 2efbb2f099fb75d95150bf2f4029b641ecbd1503 (diff) | |
i915/dp/dsc: Add Rate Control Buffer Threshold Registers
Add register defines and shifts that control the RC buffer threshold
between encoder and decoder for eDP/MIPI and DP cases.
The actual values are calculated usung a helper function.
This patch adds the shifts to registers where the value will
be written during atomic commit.
v2:
- Use _MMIO_PIPE() instead of _MMIO_(_PICK()) (Manasi)
- Combine shifts (Manasi)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1531861861-10950-3-git-send-email-anusha.srivatsa@intel.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
0 files changed, 0 insertions, 0 deletions