diff options
| author | Kevin Wang <kevin1.wang@amd.com> | 2019-07-05 15:58:46 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-05 15:59:08 -0500 |
| commit | 767acabdac81ded97e8f6930bc2dabff8db1638c (patch) | |
| tree | 5c75c09479d3c67a04472d645724e08fc8efd17d /drivers/gpu/drm/amd/amdgpu | |
| parent | e3000669a7b4b26383fad06af8f736ad3b5d161e (diff) | |
drm/amd/powerplay: add baco smu reset function for smu11
add baco reset support for smu11.
it can help gpu do asic reset when gpu recovery.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nv.c | 9 |
2 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index cec7c1fb14bf..5eeb72fcc123 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -245,8 +245,9 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, mutex_lock(&adev->mman.gtt_window_lock); gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0); - if (!adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || - adev->asic_type != CHIP_NAVI10) { + if (!adev->mman.buffer_funcs_enabled || + !adev->ib_pool_ready || + adev->in_gpu_reset) { gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0); mutex_unlock(&adev->mman.gtt_window_lock); return; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index af20ffb55c54..8e9bb6d527df 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -31,6 +31,7 @@ #include "amdgpu_vce.h" #include "amdgpu_ucode.h" #include "amdgpu_psp.h" +#include "amdgpu_smu.h" #include "atom.h" #include "amd_pcie.h" @@ -266,8 +267,14 @@ static int nv_asic_reset(struct amdgpu_device *adev) amdgpu_atombios_scratch_regs_engine_hung(adev, false); #endif + int ret = 0; + struct smu_context *smu = &adev->smu; - return 0; + if (smu_baco_is_support(smu)) { + ret = smu_baco_reset(smu); + } + + return ret; } static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) |