diff options
| author | Flora Cui <Flora.Cui@amd.com> | 2015-10-29 17:26:22 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-04 20:24:50 -0400 |
| commit | 2cea03de1040a749b2868a8a2b0c0636281c166b (patch) | |
| tree | 3d88cf1df161c901b05653491433d6e2cca8d445 /drivers/gpu/drm/amd/amdgpu | |
| parent | 60909285ef3fc62984cdcdb8e34e88fcf43c5aba (diff) | |
drm/amdgpu: add SDMA support for ELM/BAF
V2: seperate baffin & ellesmere settings instead of using fiji ones.
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index dc29a20b935b..79e5fd018a11 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -56,6 +56,11 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); +MODULE_FIRMWARE("amdgpu/ellesmere_sdma.bin"); +MODULE_FIRMWARE("amdgpu/ellesmere_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/baffin_sdma.bin"); +MODULE_FIRMWARE("amdgpu/baffin_sdma1.bin"); + static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { @@ -101,6 +106,32 @@ static const u32 fiji_mgcg_cgcg_init[] = mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; +static const u32 golden_settings_baffin_a11[] = +{ + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + +static const u32 golden_settings_ellesmere_a11[] = +{ + mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, + mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, + mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100, + mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, +}; + static const u32 cz_golden_settings_a11[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, @@ -172,6 +203,16 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; + case CHIP_BAFFIN: + amdgpu_program_register_sequence(adev, + golden_settings_baffin_a11, + (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + break; + case CHIP_ELLESMERE: + amdgpu_program_register_sequence(adev, + golden_settings_ellesmere_a11, + (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, @@ -220,6 +261,12 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; + case CHIP_BAFFIN: + chip_name = "baffin"; + break; + case CHIP_ELLESMERE: + chip_name = "ellesmere"; + break; case CHIP_CARRIZO: chip_name = "carrizo"; break; |