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authorDmitry Torokhov <[email protected]>2020-01-10 14:56:04 -0800
committerDmitry Torokhov <[email protected]>2020-01-10 14:56:04 -0800
commit1bdd3e05a0a3b4a97ea88bc46fef8fb265c8b94c (patch)
tree2244894a9ea0c941a8f32e5f3d196b4ea0eae24b /drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
parent643dd7416649bea2e8c61d8fdeeefb409a0ca5eb (diff)
parentc79f46a282390e0f5b306007bf7b11a46d529538 (diff)
Merge tag 'v5.5-rc5' into next
Sync up with mainline to get SPI "delay" API changes.
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/psp_v3_1.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/psp_v3_1.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index d2c727f6a8bd..fdc00938327b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -454,6 +454,7 @@ static int psp_v3_1_cmd_submit(struct psp_context *psp,
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
write_frame->fence_value = index;
+ amdgpu_asic_flush_hdp(adev, NULL);
/* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;