diff options
| author | Dave Airlie <airlied@redhat.com> | 2020-04-30 11:08:54 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2020-04-30 11:08:54 +1000 |
| commit | 937eea297e26effac6809a0bf8c20e6ca9d90b9a (patch) | |
| tree | 5e2d4ddc284776b56355d36c8d2c5a757956b3d4 /drivers/gpu/drm/amd/amdgpu/nv.c | |
| parent | 126a34061eec2df05a5a28052edefd4e6125f31c (diff) | |
| parent | e748f07d00c1c4a9106acafac52df7ea4ecf6264 (diff) | |
Merge tag 'amd-drm-next-5.8-2020-04-24' of git://people.freedesktop.org/~agd5f/linux into drm-next
amd-drm-next-5.8-2020-04-24:
amdgpu:
- Documentation improvements
- Enable FRU chip access on boards that support it
- RAS updates
- SR-IOV updates
- Powerplay locking fixes for older SMU versions
- VCN DPG (dynamic powergating) cleanup
- VCN 2.5 DPG enablement
- Rework GPU scheduler handling
- Improve scheduler priority handling
- Add SPM (streaming performance monitor) golden settings for navi
- GFX10 clockgating fixes
- DC ABM (automatic backlight modulation) fixes
- DC cursor and plane fixes
- DC watermark fixes
- DC clock handling fixes
- DC color management fixes
- GPU reset fixes
- Clean up MMIO access macros
- EEPROM access fixes
- Misc code cleanups
amdkfd:
- Misc code cleanups
radeon:
- Clean up safe reg list generation
- Misc code cleanups
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200424190827.4542-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nv.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nv.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 52318b03c424..995bdec9fa7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -453,18 +453,19 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) { int r; - /* Set IP register base before any HW register access */ - r = nv_reg_base_init(adev); - if (r) - return r; - adev->nbio.funcs = &nbio_v2_3_funcs; adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; - adev->nbio.funcs->detect_hw_virt(adev); - - if (amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev)) { adev->virt.ops = &xgpu_nv_virt_ops; + /* try send GPU_INIT_DATA request to host */ + amdgpu_virt_request_init_data(adev); + } + + /* Set IP register base before any HW register access */ + r = nv_reg_base_init(adev); + if (r) + return r; switch (adev->asic_type) { case CHIP_NAVI10: |