diff options
| author | Tom St Denis <tom.stdenis@amd.com> | 2015-12-01 10:42:28 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2015-12-04 11:26:50 -0500 |
| commit | 0d07db7e10f415d7ec0efde54f10a0905a0910b9 (patch) | |
| tree | 1f1bd3188f32f9939d69ceebc6d15c7c37b57add /drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |
| parent | 544b8a74c72d39aebbbf482ccad8e7762a8b2a1e (diff) | |
amdgpu/gfxv8: Simplification in gfx_v8_0_enable_gui_idle_interrupt()
Simplified the function by folding the two paths into one.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index b5396db0e6cb..33e3c0d63c66 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2818,17 +2818,11 @@ static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, { u32 tmp = RREG32(mmCP_INT_CNTL_RING0); - if (enable) { - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1); - } else { - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0); - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0); - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0); - tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0); - } + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); + WREG32(mmCP_INT_CNTL_RING0, tmp); } |