diff options
| author | Thomas Gleixner <[email protected]> | 2020-06-11 15:17:57 +0200 | 
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2020-06-11 15:17:57 +0200 | 
| commit | f77d26a9fc525286bcef3d4f98b52e17482cf49c (patch) | |
| tree | 6b179c9aa84787773cb601a14a64255e2912154b /drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | |
| parent | b6bea24d41519e8c31e4798f1c1a3f67e540c5d0 (diff) | |
| parent | f0178fc01fe46bab6a95415f5647d1a74efcad1b (diff) | |
Merge branch 'x86/entry' into ras/core
to fixup conflicts in arch/x86/kernel/cpu/mce/core.c so MCE specific follow
up patches can be applied without creating a horrible merge conflict
afterwards.
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v6_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 14 | 
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 84219534bd38..d05c39f9ae40 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2194,9 +2194,9 @@ static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)  	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);  	struct amdgpu_device *adev = crtc->dev->dev_private; -	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, -		   (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | -		   (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); +	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, +	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | +	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));  } @@ -2211,10 +2211,10 @@ static void dce_v6_0_show_cursor(struct drm_crtc *crtc)  	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,  	       lower_32_bits(amdgpu_crtc->cursor_addr)); -	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, -		   CUR_CONTROL__CURSOR_EN_MASK | -		   (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | -		   (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); +	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, +	       CUR_CONTROL__CURSOR_EN_MASK | +	       (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | +	       (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));  }  |