diff options
| author | Flora Cui <Flora.Cui@amd.com> | 2015-10-29 17:25:48 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-04 20:24:38 -0400 |
| commit | 60909285ef3fc62984cdcdb8e34e88fcf43c5aba (patch) | |
| tree | dac74c8d40461b6819620b4d8566ab164aa6d849 /drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | |
| parent | c9778572e9544b798281d57fcc92cc6a76f6a399 (diff) | |
drm/amdgpu: add DCE golden setting for ELM/BAF
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v11_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index d0eae2c41cd8..61afc5eab1b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -132,6 +132,22 @@ static const u32 stoney_golden_settings_a11[] = mmFBC_MISC, 0x1f311fff, 0x14302000, }; +static const u32 baffin_golden_settings_a11[] = +{ + mmDCI_CLK_CNTL, 0x00000080, 0x00000000, + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, + mmFBC_DEBUG1, 0xffffffff, 0x00000008, + mmFBC_MISC, 0x9f313fff, 0x14300008, + mmHDMI_CONTROL, 0x313f031f, 0x00000011, +}; + +static const u32 ellesmere_golden_settings_a11[] = +{ + mmDCI_CLK_CNTL, 0x00000080, 0x00000000, + mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, + mmFBC_MISC, 0x9f313fff, 0x14300008, + mmHDMI_CONTROL, 0x313f031f, 0x00000011, +}; static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) { @@ -149,6 +165,16 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) stoney_golden_settings_a11, (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); break; + case CHIP_BAFFIN: + amdgpu_program_register_sequence(adev, + baffin_golden_settings_a11, + (const u32)ARRAY_SIZE(baffin_golden_settings_a11)); + break; + case CHIP_ELLESMERE: + amdgpu_program_register_sequence(adev, + ellesmere_golden_settings_a11, + (const u32)ARRAY_SIZE(ellesmere_golden_settings_a11)); + break; default: break; } |