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| author | Christoph Müllner <[email protected]> | 2024-04-26 12:08:23 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2024-07-12 03:16:42 -0700 |
| commit | b8ddb0df30f9f6e70422f1e705b7416da115bd24 (patch) | |
| tree | ebea527aaf0c67a505789c0c7ff7b80f5e68a027 /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | |
| parent | 6d5852811600086f0a227a4d646b2a20b4dfe533 (diff) | |
riscv: Add Zawrs support for spinlocks
RISC-V code uses the generic ticket lock implementation, which calls
the macros smp_cond_load_relaxed() and smp_cond_load_acquire().
Introduce a RISC-V specific implementation of smp_cond_load_relaxed()
which applies WRS.NTO of the Zawrs extension in order to reduce power
consumption while waiting and allows hypervisors to enable guests to
trap while waiting. smp_cond_load_acquire() doesn't need a RISC-V
specific implementation as the generic implementation is based on
smp_cond_load_relaxed() and smp_acquire__after_ctrl_dep() sufficiently
provides the acquire semantics.
This implementation is heavily based on Arm's approach which is the
approach Andrea Parri also suggested.
The Zawrs specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Signed-off-by: Christoph Müllner <[email protected]>
Co-developed-by: Andrew Jones <[email protected]>
Signed-off-by: Andrew Jones <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h')
0 files changed, 0 insertions, 0 deletions