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authorVivek Kasireddy <[email protected]>2019-07-16 19:13:16 -0700
committerVille Syrjälä <[email protected]>2019-07-18 20:26:44 +0300
commit9a36a6517d5cc8bf7d9c1fde9058269701802e31 (patch)
treecbcc9ec9fbc117225f1ae4d8900cd526a13a712d /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
parent5270130db8c8694f7d97cc4fdc9440fb30bc2192 (diff)
drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1
Although, DPLL4 enable and disable is associated with MGPLL1_ENABLE register, we can use ICL_DPLL_CFGCR0/CR1 macros to access this dpll's CR0 and CR1 registers by passing an id of 4 to these macros. Reported-by: Ville Syrjälä <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Matt Roper <[email protected]> Cc: Imre Deak <[email protected]> Signed-off-by: Vivek Kasireddy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c')
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