diff options
| author | Shardar Shariff Md <[email protected]> | 2019-09-04 10:12:58 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2019-09-05 10:00:03 +0200 |
| commit | b9c2470fb150a3cc82a3ee8072da88cb2a73e213 (patch) | |
| tree | 6d3043b8f583e99a5d378a031c2c150f813a2f89 /drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | |
| parent | 494f79bd2365703e4093efa0ecf4b139d83aba97 (diff) | |
serial: tegra: flush the RX fifo on frame error
FIFO reset/flush code implemented now does not follow programming
guidelines. RTS line has to be turned off while flushing FIFOs to
avoid new transfers. Also check LSR bits UART_LSR_TEMT and UART_LSR_DR
to confirm FIFOs are flushed.
Signed-off-by: Shardar Shariff Md <[email protected]>
Signed-off-by: Krishna Yarlagadda <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c')
0 files changed, 0 insertions, 0 deletions