diff options
| author | vathsala nagaraju <vathsala.nagaraju@intel.com> | 2017-09-26 15:29:13 +0530 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-09-28 09:40:34 -0700 |
| commit | 977da084cc3c1791ecd6faed55e0ab41e7231660 (patch) | |
| tree | effec147002faf49e0f76016ab48cda133d4a8aa /drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | |
| parent | ae59e633b52cccf5761ac3012378fec2480c49aa (diff) | |
drm/i915/psr: Set frames before SU entry for psr2
Set frames before SU entry value for max resync frame count of
dpcd register 2009, bit field 0:3.
v2 :
- add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo)
- remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo)
- add check ==1 for dpcd_read call (ville)
v3 : (Rodrigo)
- move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU
- replace with &=
v4 :
- change the macro to shift value (jani)
- updated register names
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1506419953-32605-2-git-send-email-vathsala.nagaraju@intel.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c')
0 files changed, 0 insertions, 0 deletions