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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-08-28 10:13:33 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@kernel.org> | 2022-08-30 15:33:22 +0200 |
| commit | 4d728fd4c60e0f367321843290a618caf86b95cd (patch) | |
| tree | ef624a698b87c9a5bfe6d4db490b4b8d0a1d7230 /drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | |
| parent | 9c63902745020ca415806064ca8694b983ea436e (diff) | |
media: renesas: vsp1: Add VSP1_HAS_NON_ZERO_LBA feature bit
As per HW manual V3M and RZ/G2L SoCs has nonzero LIF buffer
attributes. So, introduce a feature bit for handling the same.
This patch also adds separate device info structure for V3M and V3H
SoCs, as both these SoCs share the same model ID, but V3H does not
have VSP1_HAS_NON_ZERO_LBA feature bit.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c')
0 files changed, 0 insertions, 0 deletions