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| author | Stanley.Yang <Stanley.Yang@amd.com> | 2022-01-21 16:50:48 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-01-25 18:00:33 -0500 |
| commit | d6dac2bc12bd968acfcec7a0c92c59d2e19dacc9 (patch) | |
| tree | b7a4269a1bcde1e17e828cdf4855c0b9efa0c98b /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |
| parent | 04022982fc5ddac6cc783d66846f2464fe4985fb (diff) | |
drm/amdgpu: fix channel index mapping for SIENNA_CICHLID
Pmfw read ecc info registers in the following order,
umc0: ch_inst 0, 1, 2 ... 7
umc1: ch_inst 0, 1, 2 ... 7
The position of the register value stored in eccinfo
table is calculated according to the below formula,
channel_index = umc_inst * channel_in_umc + ch_inst
Driver directly use the index of eccinfo table array
as channel index, it's not correct, driver needs convert
eccinfo table array index to channel index according to
channel_idx_tbl.
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
0 files changed, 0 insertions, 0 deletions