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author | Alex Deucher <alexander.deucher@amd.com> | 2018-04-02 12:29:26 -0500 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2018-04-03 13:08:46 -0500 |
commit | 41212e2fe72b26ded7ed78224d9eab720c2891e2 (patch) | |
tree | 2eeb41a5f692e59ee2bff55b89cc1071c602f777 /drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | |
parent | 85e290d92b4b794d0c758c53007eb4248d385386 (diff) |
drm/amdgpu: Fix PCIe lane width calculation
The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and
ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting
value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere.
Port of the radeon fix to amdgpu.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102553
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c')
0 files changed, 0 insertions, 0 deletions