diff options
| author | Saaem Rizvi <SyedSaaem.Rizvi@amd.com> | 2023-03-06 15:10:13 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-03-22 00:48:01 -0400 |
| commit | 74fa4c81aadf418341f0d073c864ea7dca730a2e (patch) | |
| tree | 0443ba81f62057c2c1e9fb2eea407b797b515461 /drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c | |
| parent | cfa075982768840c468c874219dbec558722cb7f (diff) | |
drm/amd/display: Implement workaround for writing to OTG_PIXEL_RATE_DIV register
[Why and How]
Current implementation requires FPGA builds to take a different
code path from DCN32 to write to OTG_PIXEL_RATE_DIV. Now that
we have a workaround to write to OTG_PIXEL_RATE_DIV register without
blanking display on hotplug on DCN32, we can allow the code paths for
FPGA to be exactly the same allowing for more consistent
testing.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c')
0 files changed, 0 insertions, 0 deletions