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authorPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>2024-06-03 10:46:10 +0200
committerAlex Deucher <alexander.deucher@amd.com>2024-06-27 17:09:46 -0400
commitc71c9aafd5faa579e6ffe32018071c7af97d5a2e (patch)
tree9e1acf150eab293664811f85d626f538986a12c9 /drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
parente779af8e8b51b4b3d403fa002e579b56b1931296 (diff)
amdgpu: don't dereference a NULL resource in sysfs code
dma_resv_trylock being successful doesn't guarantee that bo->tbo.base.resv is not NULL, so check its validity before using it. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_object.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c63
1 files changed, 33 insertions, 30 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index fa5227a4aac2..08e53dacdad9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1601,36 +1601,39 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
u64 size;
if (dma_resv_trylock(bo->tbo.base.resv)) {
-
- switch (bo->tbo.resource->mem_type) {
- case TTM_PL_VRAM:
- if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
- placement = "VRAM VISIBLE";
- else
- placement = "VRAM";
- break;
- case TTM_PL_TT:
- placement = "GTT";
- break;
- case AMDGPU_PL_GDS:
- placement = "GDS";
- break;
- case AMDGPU_PL_GWS:
- placement = "GWS";
- break;
- case AMDGPU_PL_OA:
- placement = "OA";
- break;
- case AMDGPU_PL_PREEMPT:
- placement = "PREEMPTIBLE";
- break;
- case AMDGPU_PL_DOORBELL:
- placement = "DOORBELL";
- break;
- case TTM_PL_SYSTEM:
- default:
- placement = "CPU";
- break;
+ if (!bo->tbo.resource) {
+ placement = "NONE";
+ } else {
+ switch (bo->tbo.resource->mem_type) {
+ case TTM_PL_VRAM:
+ if (amdgpu_res_cpu_visible(adev, bo->tbo.resource))
+ placement = "VRAM VISIBLE";
+ else
+ placement = "VRAM";
+ break;
+ case TTM_PL_TT:
+ placement = "GTT";
+ break;
+ case AMDGPU_PL_GDS:
+ placement = "GDS";
+ break;
+ case AMDGPU_PL_GWS:
+ placement = "GWS";
+ break;
+ case AMDGPU_PL_OA:
+ placement = "OA";
+ break;
+ case AMDGPU_PL_PREEMPT:
+ placement = "PREEMPTIBLE";
+ break;
+ case AMDGPU_PL_DOORBELL:
+ placement = "DOORBELL";
+ break;
+ case TTM_PL_SYSTEM:
+ default:
+ placement = "CPU";
+ break;
+ }
}
dma_resv_unlock(bo->tbo.base.resv);
} else {