Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-next

- lots of code cleanup
- lots of bug fixes
- expose rpm based fan info via hwmon
- lots of clock and powergating fixes
- SI register header cleanup and conversion to common format used by newer asics

* 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (54 commits)
  drm/amdgpu: drop is_display_hung from display funcs
  drm/amdgpu/uvd: reduce IB parsing overhead on UVD5+ (v2)
  drm/amdgpu/uvd: consolidate code for fetching addr from ctx
  drm/amdgpu: Disable DPM in virtualization
  drm/amdgpu: use AMDGPU_GEM_CREATE_VRAM_CLEARED for VM PD/PTs (v2)
  drm/amdgpu: improve AMDGPU_GEM_CREATE_VRAM_CLEARED handling (v2)
  drm/amdgpu: fix error handling in amdgpu_bo_create_restricted
  drm/amdgpu: fix amdgpu_fill_buffer (v2)
  drm/amdgpu: remove amdgpu_irq_get_delayed
  amdgpu: Wrap dev_err() calls on vm faults with printk_ratelimit()
  amdgpu: Use dev_err() over vanilla printk() in vm_decode_fault()
  drm/amd/amdgpu: port of DCE v6 to new headers (v3)
  drm/amdgpu: cleanup unused iterator members for sdma v2.4
  drm/amdgpu: cleanup unused iterator members for sdma v3
  drm/amdgpu:impl vgt_flush for VI(V5)
  drm/amdgpu: enable uvd mgcg for Fiji.
  drm/amdgpu: refine cz uvd clock gate logic.
  drm/amdgpu: change log level to KERN_INFO in ci_dpm.c
  drm/amdgpu: always un-gate UVD REGS path.
  drm/amdgpu/sdma: fix typo in packet setup
  ...

1 files changed, 16 insertions, 31 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1479d09bd4dd..bf79b73e1538 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -128,17 +128,6 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
 		if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 			lpfn = adev->mc.real_vram_size >> PAGE_SHIFT;
 
-		if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
-		    !(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
-		    adev->mc.visible_vram_size < adev->mc.real_vram_size) {
-			places[c].fpfn = visible_pfn;
-			places[c].lpfn = lpfn;
-			places[c].flags = TTM_PL_FLAG_WC |
-				TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM |
-				TTM_PL_FLAG_TOPDOWN;
-			c++;
-		}
-
 		places[c].fpfn = 0;
 		places[c].lpfn = lpfn;
 		places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
@@ -382,39 +371,36 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 
 	amdgpu_fill_placement_to_bo(bo, placement);
 	/* Kernel allocation are uninterruptible */
+
+	if (!resv) {
+		bool locked;
+
+		reservation_object_init(&bo->tbo.ttm_resv);
+		locked = ww_mutex_trylock(&bo->tbo.ttm_resv.lock);
+		WARN_ON(!locked);
+	}
 	r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
 			&bo->placement, page_align, !kernel, NULL,
-			acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
-	if (unlikely(r != 0)) {
+			acc_size, sg, resv ? resv : &bo->tbo.ttm_resv,
+			&amdgpu_ttm_bo_destroy);
+	if (unlikely(r != 0))
 		return r;
-	}
 
 	if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 	    bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 		struct dma_fence *fence;
 
-		if (adev->mman.buffer_funcs_ring == NULL ||
-		   !adev->mman.buffer_funcs_ring->ready) {
-			r = -EBUSY;
-			goto fail_free;
-		}
-
-		r = amdgpu_bo_reserve(bo, false);
-		if (unlikely(r != 0))
-			goto fail_free;
-
-		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
-		r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
-		if (unlikely(r != 0))
+		r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
+		if (unlikely(r))
 			goto fail_unreserve;
 
-		amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 		amdgpu_bo_fence(bo, fence, false);
-		amdgpu_bo_unreserve(bo);
 		dma_fence_put(bo->tbo.moving);
 		bo->tbo.moving = dma_fence_get(fence);
 		dma_fence_put(fence);
 	}
+	if (!resv)
+		ww_mutex_unlock(&bo->tbo.resv->lock);
 	*bo_ptr = bo;
 
 	trace_amdgpu_bo_create(bo);
@@ -422,8 +408,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 	return 0;
 
 fail_unreserve:
-	amdgpu_bo_unreserve(bo);
-fail_free:
+	ww_mutex_unlock(&bo->tbo.resv->lock);
 	amdgpu_bo_unref(&bo);
 	return r;
 }