diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-05-23 17:33:34 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-06-15 17:24:12 -0700 |
| commit | 723e367114dec95abe8bba4118c4c7c3542a463f (patch) | |
| tree | c849163e4c82a05ead01bd55361052cc473c9cf5 /drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | |
| parent | 2d2a2900588cabe2ff3abd552d1683e5f1ce398b (diff) | |
clk: mediatek: reset: Support nonsequence base offsets of reset registers
The bank offsets are not serial for all reset registers.
For example, there are five infra reset banks for MT8192: 0x120, 0x130,
0x140, 0x150 and 0x730.
To support this,
- Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of
the reset register.
- Add a new define RST_NR_PER_BANK to define reset number for each
reset bank.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c')
0 files changed, 0 insertions, 0 deletions