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authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>2022-08-30 15:16:40 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-09-19 15:09:44 -0400
commit62f0576c42993a442ae722fe2e67a140e4669945 (patch)
tree9323fb825098b2a333bc7de67b7fe72c71668827 /drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
parent22c42b0ec225c92db33e4b3045ad15baf1427cff (diff)
drm/amd/display: fix dcn315 memory channel count and width read
[Why & How] Correctly set ddr5 channel width to 8 bytes Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c')
0 files changed, 0 insertions, 0 deletions