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| author | José Roberto de Souza <jose.souza@intel.com> | 2021-05-14 16:22:45 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-06-07 11:01:29 -0700 |
| commit | 6d7a793aabf31d7ba2b16fc13a94ccf0b90e4be0 (patch) | |
| tree | cf268cb02a934e2288fb7693ed774e4b86430367 /drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | |
| parent | 9b2e49a14838584b659548565b799e0523659295 (diff) | |
drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled
When PSR is enabled it handles DP_SDP_VSC, changing revision and all
the other fields as necessary.
It can also enabled and disable this SDP as needed without a full
modeset.
So here masking DP_SDP_VSC bit when previous and future state PSR
enabled, it will still be checked when comparing the asked state
to what was programmed to hardware.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210514232247.144542-2-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h')
0 files changed, 0 insertions, 0 deletions